GPIO Pin Map

Cross-referenced from live gpio dir/gpio regs queries (2026-02-13), K60 datasheet pin mux table (MK60DN512VLQ10, 144-LQFP), boot log peripheral init, and A3981 datasheet.

SPI1 — A3981 Stepper Motor Drivers (4 MHz, mode 0x03)

The two A3981 stepper motor driver ICs are controlled via SPI1 at 4 MHz. SPI mode 0x03 means CPOL=1, CPHA=1.

K60 Pin	GPIO	Alt	Function	Dir	State	Notes
PTE0	E0	ALT2	SPI1_PCS1	OUT	1	A3981 #2 chip select (EL motor)
PTE1	E1	ALT2	SPI1_SOUT	(periph)	1	MOSI — MCU to A3981
PTE2	E2	ALT2	SPI1_SCK	(periph)	1	SPI clock
PTE3	E3	ALT2	SPI1_SIN	(periph)	0	MISO — A3981 to MCU
PTE4	E4	ALT2	SPI1_PCS0	IN*	1	A3981 #1 chip select (AZ motor)
PTE5	E5	ALT2	SPI1_PCS2	OUT	1	Possibly A3981 RESET or enable

Note

PTE4 shows INPUT in the GPIO dir register, but this is irrelevant when muxed to the SPI peripheral. The SPI controller manages chip select assertion/deassertion directly.

SPI2 — BCM4515 DVB-S2 Tuner (6.857 MHz, mode 0x03)

The BCM4515 DVB-S2 tuner communicates via SPI2. The clock frequency is 48 MHz / 7 = 6.857 MHz.

K60 Pin	GPIO	Alt	Function	Dir	State	Notes
PTD11	D11	ALT2	SPI2_PCS0	OUT	1	BCM4515 chip select
PTD12	D12	ALT2	SPI2_SCK	IN*	1	SPI clock
PTD13	D13	ALT2	SPI2_SOUT	IN*	1	MOSI — MCU to BCM4515
PTD14	D14	ALT2	SPI2_SIN	—	0	MISO — BCM4515 to MCU
PTD15	D15	ALT2	SPI2_PCS1	—	0	Secondary chip select (unused?)

Note

GPIO dir register values are not meaningful for peripheral-muxed pins. The SPI controller drives these pins regardless of the GPIO direction setting.

UART4 — RS-422 Console (115200 baud)

The console serial port used for all firmware interaction.

K60 Pin	GPIO	Alt	Function	Dir	State	Notes
PTE24	E24	ALT3	UART4_TX	OUT	1	Console TX (to computer RX pair)
PTE25	E25	ALT3	UART4_RX	IN	1	Console RX (from computer TX pair)
PTE26	E26	ALT3	UART4_CTS	IN	1	Hardware flow control (idle high)
PTE27	E27	—	GPIO	IN	1	Unknown (RTS? or pullup)
PTE28	E28	—	GPIO	IN	1	Unknown

DIP Switch GPIOs

The dipswitch command reads the raw value val:ffffff01 (all OFF/up), which maps to app_dipswitch:101 (DISH 110+119+129 degrees W).

Exact GPIO pins are TBD — likely Port A or Port C inputs with internal pullups. The 0xffffff01 raw value suggests a 32-bit register read where bits 1-24 are all high (pullup, switches open) and bit 0 is high (LSB).

A3981 Diagnostic Pins

The a3981 diag command reads fault status from two GPIO pins (one per motor driver). Both read “OK” when motors are healthy. The A3981 DIAG output is active-low open-drain, pulled high when no fault is present.

Exact GPIO pins are TBD — likely on Port A or Port E near the SPI1 bus.

Unidentified High-State Outputs

These GPIO pins were observed in the HIGH state (logic 1) during the gpio regs dump. Their functions are inferred from context and K60 pin mux options.

GPIO	Dir	State	Likely Function
D10	OUT	1	BCM4515 reset or power enable
B0-B3	—	1	SPI0 or I2C bus (B0-B3 cluster)
B11	—	1	Status LED or peripheral enable
C10-C13	—	1	Contiguous block — possibly bus interface
C18	—	1	LNB voltage control or relay

Full GPIO Register Summary

From the gpio regs command, 101 pins are enumerated across 5 ports:

Port	Pins Enumerated	Count	High Pins (=1)
A	A0-A19, A24-A29	26	A1, A3, A4, A5, A15, A16, A25-A29
B	B0-B11, B16-B23	20	B0, B1, B2, B3, B11
C	C0-C19	20	C10, C11, C12, C13, C18
D	D0-D15	16	D11, D12, D13
E	E0-E12, E24-E29	19	E0, E1, E2, E4, E5, E7, E9-E12, E24-E28

Note

Pins A20-A23 and B12-B15 are not enumerated (reserved or unbonded on the 144-LQFP package). E29 shows “Unknown bit E29” in the firmware output — the pin is defined in hardware but not assigned a function.

USB Port Pins (Potentially Accessible)

The K60 has dedicated USB pins that cannot be muxed to GPIO:

LQFP Pin	Signal	Function
19	USB0_DP	USB Data+
20	USB0_DM	USB Data-
21	VOUT33	USB VREG 3.3V output
22	VREGIN	USB VREG 5V input (self-power from USB)

The Trav’ler Pro uses USB A-to-A (ttyACM0) for its serial console, proving Winegard has USB CDC/ACM firmware for the Kinetis platform. The G2 may also have a USB connector on the PCB (possibly internal, for field service). NVS indices 2 (“Debug 2nd Console Port”) and 4 (“Debug Port Connection”) hint at multiple console port support.

SWD / Debug Interface Pins

For firmware extraction via SWD debug probe:

Signal	K60 Pin	LQFP-144	Notes
SWDIO	PTA3	Pin 50	Bidirectional data
SWDCLK	PTA0	Pin 46	Clock (probe drives)
GND	—	Multiple	Common ground with probe
RESET	—	Pin 74	Optional but recommended
SWO	PTA2	Pin 49	Optional trace output